top.vhd (1325B)
1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 18.09.2025 19:42:42 6 -- Design Name: 7 -- Module Name: top - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool Versions: 11 -- Description: 12 -- 13 -- Dependencies: 14 -- 15 -- Revision: 16 -- Revision 0.01 - File Created 17 -- Additional Comments: 18 -- 19 ---------------------------------------------------------------------------------- 20 21 22 library IEEE; 23 use IEEE.STD_LOGIC_1164.ALL; 24 25 -- Uncomment the following library declaration if using 26 -- arithmetic functions with Signed or Unsigned values 27 --use IEEE.NUMERIC_STD.ALL; 28 29 -- Uncomment the following library declaration if instantiating 30 -- any Xilinx leaf cells in this code. 31 --library UNISIM; 32 --use UNISIM.VComponents.all; 33 34 entity top is 35 port ( 36 clk : in std_logic; 37 io_btn0 : in std_logic; 38 led0 : out std_logic 39 ); 40 end top; 41 42 architecture Behavioral of top is 43 44 signal r_led0 : std_logic := '0'; 45 signal r_btn0 : std_logic := '0'; 46 47 begin 48 49 process (clk) is 50 begin 51 if rising_edge (clk) then 52 r_btn0 <= io_btn0; 53 if io_btn0 = '0' and r_btn0 = '1' then 54 r_led0 <= not r_led0; 55 end if; 56 end if; 57 end process; 58 59 led0 <= r_led0; 60 61 end Behavioral;