commit 09da5965b7937aeca64438a57ecbd875f617a182
parent 251b1a834f1c0503104d803089368eb7dd866622
Author: William Lindholm <william_lindholm@outlook.com>
Date: Sun, 21 Sep 2025 22:27:39 +0200
Added some testing for project
Diffstat:
2 files changed, 113 insertions(+), 20 deletions(-)
diff --git a/buttons_to_leds/buttons_to_leds.srcs/testbenches/new/top_tb.vhd b/buttons_to_leds/buttons_to_leds.srcs/testbenches/new/top_tb.vhd
@@ -0,0 +1,89 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21.09.2025 21:26:10
+-- Design Name:
+-- Module Name: top_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_tb is
+end top_tb;
+
+architecture Behavioral of top_tb is
+signal s_led0, s_led1, s_led2, s_led3, s_led4, s_led5, s_led6, s_led7 : std_logic;
+signal s_io_btn0, s_io_btn1, s_io_btn2, s_io_btn3, s_io_btn4 : std_logic;
+begin
+
+ UUT : entity work.top
+ port map (
+ led0 => s_led0,
+ led1 => s_led1,
+ led2 => s_led2,
+ led3 => s_led3,
+ led4 => s_led4,
+ led5 => s_led5,
+ led6 => s_led6,
+ led7 => s_led7,
+ io_btn0 => s_io_btn0,
+ io_btn1 => s_io_btn1,
+ io_btn2 => s_io_btn2,
+ io_btn3 => s_io_btn3,
+ io_btn4 => s_io_btn4
+ );
+
+ process is
+ begin
+ -- initialize default button signals
+ s_io_btn0 <= '0';
+ s_io_btn1 <= '0';
+ s_io_btn2 <= '0';
+ s_io_btn3 <= '0';
+ s_io_btn4 <= '0';
+ wait for 10 ns;
+
+ -- Test default state of LEDs
+ assert s_led0 = '0' report "Default state of led0 not off" severity error;
+ assert s_led1 = '0' report "Default state of led1 not off" severity error;
+ assert s_led2 = '0' report "Default state of led2 not off" severity error;
+ assert s_led3 = '0' report "Default state of led3 not off" severity error;
+ assert s_led4 = '0' report "Default state of led4 not off" severity error;
+ assert s_led5 = '0' report "Default state of led5 not off" severity error;
+ assert s_led6 = '0' report "Default state of led6 not off" severity error;
+ assert s_led7 = '1' report "Default state of led7 not on" severity error;
+
+ -- Test behaviour of LED0
+ s_io_btn0 <= '1';
+ wait for 10 ns;
+ assert s_led0 = '1' report "led0 did not turn on when pressing io_btn0" severity error;
+ assert s_led6 = '1' report "led6 did not turn on when pressing io_btn0" severity error;
+
+ wait; -- keep simulation running
+ end process;
+ -- assert led0 on when io_btn0 is pressed
+
+end Behavioral;
diff --git a/buttons_to_leds/buttons_to_leds.xpr b/buttons_to_leds/buttons_to_leds.xpr
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2025.1 (64-bit) -->
+<!-- Product Version: Vivado v2025.1.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
@@ -45,7 +45,7 @@
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
- <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="ActiveSimSet" Val="testbenches"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
@@ -59,7 +59,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="1"/>
+ <Option Name="WTXSimLaunchSim" Val="6"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -114,11 +114,29 @@
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
- <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
- <Filter Type="Srcs"/>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="testbenches" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/testbenches" RelGenDir="$PGENDIR/testbenches">
+ <File Path="$PSRCDIR/testbenches/new/top_tb.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="top"/>
+ <Option Name="TopModule" Val="top_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
@@ -135,20 +153,6 @@
<Option Name="Dmv" Val=""/>
</Config>
</FileSet>
- <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
- <Filter Type="Utils"/>
- <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedInSteps" Val="synth_1"/>
- <Attr Name="AutoDcp" Val="1"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
