fpga_labs

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commit 454f782d0c877d9589d6d881d3f2bf2c2511c6b4
parent 3cbdbe60696471aacf8f99e7ee66a818fbcb46c7
Author: William Lindholm <85635561+LindholmLabs@users.noreply.github.com>
Date:   Wed, 17 Sep 2025 19:55:07 +0200

Update README.md
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MREADME.md | 2++


1 file changed, 2 insertions(+), 0 deletions(-)

diff --git a/README.md b/README.md
@@ -2,3 +2,5 @@
 - Alchitry Platinum v2 - [schematic](https://cdn.alchitry.com/docs/Pt-V2/Alchitry%20Platinum%20Rev%20A.pdf)
 - Alchitry Platinum v2 - [connector positions](https://cdn.alchitry.com/docs/Au-V2/AuDrawing.pdf)
 - Alchitry IO v2 - [schematic](https://cdn.alchitry.com/docs/Io-V2/IoSchematic.pdf)
+- Xilinx Artix 7 - [SelectIO](https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO)
+- Xilinx Artix 7 - [DC and AC Switching Characteristics](https://docs.amd.com/v/u/en-US/ds181_Artix_7_Data_Sheet)