fpga_labs

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commit 8439005c88b455eb702240f3c4f67afb593649ad
parent b9eb8a130a03a3cbbd767951f9a335a7dd92351e
Author: William Lindholm <85635561+LindholmLabs@users.noreply.github.com>
Date:   Wed, 17 Sep 2025 22:45:25 +0200

Added link to first batch pinout
Diffstat:

MREADME.md | 1+


1 file changed, 1 insertion(+), 0 deletions(-)

diff --git a/README.md b/README.md
@@ -1,6 +1,7 @@
 # HARDWARE RESOURCES
 - Alchitry Platinum v2 - [schematic](https://cdn.alchitry.com/docs/Pt-V2/Alchitry%20Platinum%20Rev%20A.pdf)
 - Alchitry Platinum v2 - [connector positions](https://cdn.alchitry.com/docs/Au-V2/AuDrawing.pdf)
+- Alchitry Platinum v2 First Batch - [pinout](https://github.com/alchitry/Alchitry-Labs-V2/blob/master/src/main/kotlin/com/alchitry/labs2/hardware/pinout/PtV2AlphaTopPin.kt)
 - Alchitry IO v2 - [schematic](https://cdn.alchitry.com/docs/Io-V2/IoSchematic.pdf)
 - Xilinx Artix 7 - [SelectIO](https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO)
 - Xilinx Artix 7 - [DC and AC Switching Characteristics](https://docs.amd.com/v/u/en-US/ds181_Artix_7_Data_Sheet)