commit b4470d626a1f6c6f35bd216f0de9e54412baaeae parent e12ada82998f0b05250d01d6f8c34d0fdd6be8d1 Author: William Lindholm <william_lindholm@outlook.com> Date: Fri, 19 Sep 2025 20:49:24 +0200 Upload toggle LED project Diffstat:
| A | alchitry_platinum_v2_first_batch_with_io_v2.xdc | | | 22 | ++++++++++++++++++++++ |
| M | buttons_to_leds/buttons_to_leds.srcs/sources_1/new/top.vhd | | | 4 | ++-- |
| A | toggle_led/toggle_led.srcs/sources_1/new/top.vhd | | | 61 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | toggle_led/toggle_led.xpr | | | 407 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
4 files changed, 492 insertions(+), 2 deletions(-)
diff --git a/alchitry_platinum_v2_first_batch_with_io_v2.xdc b/alchitry_platinum_v2_first_batch_with_io_v2.xdc @@ -0,0 +1,21 @@ +# LEDs +set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports {led0}] +set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports {led1}] +set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports {led2}] +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports {led3}] +set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports {led4}] +set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports {led5}] +set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports {led6}] +set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports {led7}] + +# BUTTONs +set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports {io_btn0}] +set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports {io_btn1}] +set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {io_btn2}] +set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {io_btn3}] +set_property -dict { PACKAGE_PIN L4 IOSTANDARD LVCMOS33 } [get_ports {io_btn4}] + +# PERIPHERALs +set_property PACKAGE_PIN W19 [get_ports {clk}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk}] +create_clock -name clk -period 10.0 [get_ports {clk}] +\ No newline at end of file diff --git a/buttons_to_leds/buttons_to_leds.srcs/sources_1/new/top.vhd b/buttons_to_leds/buttons_to_leds.srcs/sources_1/new/top.vhd @@ -48,8 +48,8 @@ begin led2 <= io_btn2; led3 <= io_btn3; led4 <= io_btn4; - led5 <= '1'; - led6 <= '1'; + led5 <= io_btn0 and io_btn3; + led6 <= io_btn0 or io_btn3; led7 <= '1'; end Behavioral; \ No newline at end of file diff --git a/toggle_led/toggle_led.srcs/sources_1/new/top.vhd b/toggle_led/toggle_led.srcs/sources_1/new/top.vhd @@ -0,0 +1,61 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18.09.2025 19:42:42 +-- Design Name: +-- Module Name: top - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity top is + port ( + clk : in std_logic; + io_btn0 : in std_logic; + led0 : out std_logic + ); +end top; + +architecture Behavioral of top is + +signal r_led0 : std_logic := '0'; +signal r_btn0 : std_logic := '0'; + +begin + + process (clk) is + begin + if rising_edge (clk) then + r_btn0 <= io_btn0; + if io_btn0 = '0' and r_btn0 = '1' then + r_led0 <= not r_led0; + end if; + end if; + end process; + + led0 <= r_led0; + +end Behavioral; diff --git a/toggle_led/toggle_led.xpr b/toggle_led/toggle_led.xpr @@ -0,0 +1,407 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2025.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<Project Product="Vivado" Version="7" Minor="70" Path="C:/Users/Willi/Documents/repos/fpga_labs/toggle_led/toggle_led.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="51b577a8f7a64b4a88c6fac89d11b533"/> + <Option Name="Part" Val="xc7a100tfgg484-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2025.1"/> + <Option Name="SimulatorVersionModelSim" Val="2024.3"/> + <Option Name="SimulatorVersionQuesta" Val="2024.3_3"/> + <Option Name="SimulatorVersionXcelium" Val="24.09.001"/> + <Option Name="SimulatorVersionVCS" Val="W-2024.09-SP1"/> + <Option Name="SimulatorVersionRiviera" Val="2024.10"/> + <Option Name="SimulatorVersionActiveHdl" Val="15.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="TargetLanguage" Val="VHDL"/> + <Option Name="BoardPart" Val=""/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="WTXSimLaunchSim" Val="1"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="UseInlineHdlIP" Val="TRUE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="32"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/top.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PPRDIR/../alchitry_platinum_v2_first_batch_with_io_v2.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + <Option Name="CosimPdi" Val=""/> + <Option Name="CosimPlatform" Val=""/> + <Option Name="CosimElf" Val=""/> + <Option Name="Dmv" Val=""/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + <Simulator Name="ActiveHDL"> + <Option Name="Description" Val="Active-HDL Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="22"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2025"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tfgg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2025"/> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2025"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="10"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:9] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="11"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:13] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="12"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:14] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="13"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:15] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="14"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:16] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="4"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:3] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="5"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:4] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="6"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:5] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="7"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:6] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="8"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:7] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <MsgRule> + <MsgAttr Name="RuleType" Val="0"/> + <MsgAttr Name="Limit" Val="-1"/> + <MsgAttr Name="NewSeverity" Val="ANY"/> + <MsgAttr Name="Id" Val="Common 17-55"/> + <MsgAttr Name="Severity" Val="ANY"/> + <MsgAttr Name="ShowRule" Val="1"/> + <MsgAttr Name="RuleSource" Val="8"/> + <MsgAttr Name="StringIsRegExp" Val="0"/> + <MsgAttr Name="RuleId" Val="9"/> + <MsgAttr Name="Note" Val=""/> + <MsgAttr Name="Author" Val=""/> + <MsgAttr Name="CreatedTimestamp" Val=""/> + <MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Willi/Documents/repos/fpga_labs/alchitry_platinum_v2_first_batch_with_io_v2.xdc:8] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object."/> + </MsgRule> + <Board/> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project>